Symbol: TMLD_REG_DBG_FORCE_FRAME
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
51334
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
46814
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL //Access:RW DataWidth:0x4 DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift). Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
50116
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
50116
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
50116
#define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).