Symbol: TCM_REG_PRS_LENGTH_MIS
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
16436
#define TCM_REG_PRS_LENGTH_MIS 0x50168UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#6 interface.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
66456
#define TCM_REG_PRS_LENGTH_MIS 0x1180ab4UL //Access:RC DataWidth:0x1 Set at message length mismatch (relative to last indication) at PRS interface. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
70129
#define TCM_REG_PRS_LENGTH_MIS 0x1180ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PRS interface.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
70129
#define TCM_REG_PRS_LENGTH_MIS 0x1180ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PRS interface.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
70129
#define TCM_REG_PRS_LENGTH_MIS 0x1180ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PRS interface.