TCM_REG_AGG_TASK_CTX
#define TCM_REG_AGG_TASK_CTX 0x11814c8UL //Access:RW DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
#define TCM_REG_AGG_TASK_CTX 0x11814c8UL //Access:RW DataWidth:0x20 Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0. Chips: BB_A0 BB_B0 K2
#define TCM_REG_AGG_TASK_CTX 0x11814c8UL //Access:RW DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
#define TCM_REG_AGG_TASK_CTX 0x11814c8UL //Access:RW DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.
#define TCM_REG_AGG_TASK_CTX 0x11814c8UL //Access:RW DataWidth:0x20 // Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.