SEM_FAST_REG_DEBUG_MODE
#define SEM_FAST_REG_DEBUG_MODE 0x18b00UL //ACCESS:RW DataWidth:0x3 Description: debug mode (0-store to 0x7000; 1-pram_addr; 2-foc ready; 3-(b[31int; b[30:16-int_add;b[15-dra_rd; b[14-dra_rd_set; b[13:8-dra_rd_addr; b[7dra_wr; b[6dra_wr_set; b[5:0dra_wr_addr); 4- (dmem_wr[17; dmem_rd[16; dmem_add[15:0); 5-(int_rbc_cur_state[5:4; 1'b0; wr_rbc_cur_state[2:0); 6-recording handlers. This register is not applicable when ~debug_active =0
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL //Access:RW DataWidth:0x3 // Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7- Performance monitor. Note: this register is not applicable when DebugActive=0.
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL //Access:RW DataWidth:0x3 Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7-Reserved. Note: this register is not applicable when DebugActive=0. Chips: BB_A0 BB_B0 K2
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL //Access:RW DataWidth:0x3 // Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7-Reserved. Note: this register is not applicable when DebugActive=0.
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL //Access:RW DataWidth:0x3 // Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7-Reserved. Note: this register is not applicable when DebugActive=0.
#define SEM_FAST_REG_DEBUG_MODE 0x000744UL //Access:RW DataWidth:0x3 // Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7-Reserved. Note: this register is not applicable when DebugActive=0.