SEM_FAST_REG_DBG_MODE6_SRC_DISABLE
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x18ec0UL //ACCESS:RW DataWidth:0x7 Description: Disable register for each output of ~debug_mode=6 : b0-dra_in disable; b1-fin disable; b2-load disable;b3-pram disable;b4-ext storedisable; b5-other store disable; ; b6-vfc store disable)
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL //Access:RW DataWidth:0x6 // Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable.
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL //Access:RW DataWidth:0x6 Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable. Chips: BB_A0 BB_B0 K2
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL //Access:RW DataWidth:0x6 // Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable.
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL //Access:RW DataWidth:0x6 // Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable.
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL //Access:RW DataWidth:0x6 // Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable.