Symbol: RSS_REG_RSS_RAM_ADDR
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
41554
#define RSS_REG_RSS_RAM_ADDR 0x238c30UL //Access:RW DataWidth:0xd // RSS RAM address. If bit 12 is 1 then bits 11:0 is done to RSS indirection memory If bits 12:10 is 0 then bits 6:0 is address to RSS CID table; If bits 12:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 12:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 12:10 is 3 then bits 7:0 is address to RSS INFO table.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
37493
#define RSS_REG_RSS_RAM_ADDR 0x238c30UL //Access:RW DataWidth:0xd RSS RAM address. If bit 12 is 0 then access is done to RSS memory according to 12 LSB bits. If bit 12 is 1 then access is done to RSS indirection memory according to 12 LSB bits : If bits 11:10 is 0 then bits 9:0 is address to RSS CID table; If bits 11:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 11:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 11:10 is 3 then bits 9:0 is address to RSS INFO table. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
40610
#define RSS_REG_RSS_RAM_ADDR 0x238c30UL //Access:RW DataWidth:0xd // RSS RAM address. If bit 12 is 0 then access is done to RSS memory according to 12 LSB bits. If bit 12 is 1 then access is done to RSS indirection memory according to 12 LSB bits : If bits 11:10 is 0 then bits 9:0 is address to RSS CID table; If bits 11:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 11:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 11:10 is 3 then bits 9:0 is address to RSS INFO table.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
40610
#define RSS_REG_RSS_RAM_ADDR 0x238c30UL //Access:RW DataWidth:0xd // RSS RAM address. If bit 12 is 1 then bits 11:0 is done to RSS indirection memory If bits 12:10 is 0 then bits 6:0 is address to RSS CID table; If bits 12:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 12:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 12:10 is 3 then bits 7:0 is address to RSS INFO table.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
40610
#define RSS_REG_RSS_RAM_ADDR 0x238c30UL //Access:RW DataWidth:0xd // RSS RAM address. If bit 12 is 0 then access is done to RSS memory according to 12 LSB bits. If bit 12 is 1 then access is done to RSS indirection memory according to 12 LSB bits : If bits 11:10 is 0 then bits 9:0 is address to RSS CID table; If bits 11:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 11:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 11:10 is 3 then bits 9:0 is address to RSS INFO table.