Symbol: QM_REG_SOFT_RESET
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
15005
#define QM_REG_SOFT_RESET 0x168428UL //ACCESS:RW DataWidth:0x1 Description: Initialization bit command
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
47040
#define QM_REG_SOFT_RESET 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
43139
#define QM_REG_SOFT_RESET 0x2f2c00UL //Access:RW DataWidth:0x1 Initialization bit command. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
46021
#define QM_REG_SOFT_RESET 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
46021
#define QM_REG_SOFT_RESET 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
46021
#define QM_REG_SOFT_RESET 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.