QM_REG_RLGLBLCRD
#define QM_REG_RLGLBLCRD 0x2f4400UL //Access:RW DataWidth:0x20 // The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
#define QM_REG_RLGLBLCRD 0x2f4400UL //Access:RW DataWidth:0x20 The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation Chips: BB_A0 BB_B0 K2
#define QM_REG_RLGLBLCRD 0x2f4400UL //Access:RW DataWidth:0x20 // The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
#define QM_REG_RLGLBLCRD 0x2f4400UL //Access:RW DataWidth:0x20 // The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation
#define QM_REG_RLGLBLCRD 0x2f4400UL //Access:RW DataWidth:0x20 // The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation