Symbol: PSWWR_REG_DBG_DWORD_ENABLE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
43023
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
38839
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL //Access:RW DataWidth:0x4 DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
42055
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
42055
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
42055
#define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output