Symbol: PSWRQ2_REG_WR_MBS0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
42057
#define PSWRQ2_REG_WR_MBS0 0x240400UL //Access:RW DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
37891
#define PSWRQ2_REG_WR_MBS0 0x240400UL //Access:RW DataWidth:0x3 Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
41091
#define PSWRQ2_REG_WR_MBS0 0x240400UL //Access:RW DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
41091
#define PSWRQ2_REG_WR_MBS0 0x240400UL //Access:RW DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
41091
#define PSWRQ2_REG_WR_MBS0 0x240400UL //Access:RW DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;.