Symbol: PSWHST_REG_VF_DISABLED_ERROR_DATA
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44009
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL //Access:R DataWidth:0x12 // The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
39843
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL //Access:R DataWidth:0x12 The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43041
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL //Access:R DataWidth:0x12 // The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43041
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL //Access:R DataWidth:0x12 // The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43041
#define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL //Access:R DataWidth:0x12 // The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.