Symbol: PSWHST_REG_INCORRECT_ACCESS_LENGTH
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44013
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL //Access:R DataWidth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
39847
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL //Access:R DataWidth:0x7 The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43045
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL //Access:R DataWidth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43045
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL //Access:R DataWidth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43045
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL //Access:R DataWidth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.