Symbol: CAU_REG_SB_VAR_MEMORY
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
39037
#define CAU_REG_SB_VAR_MEMORY 0x1c6000UL //Access:WB DataWidth:0x40 // Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones); the memory will receive the follow
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
35336
#define CAU_REG_SB_VAR_MEMORY 0x1c6000UL //Access:WB DataWidth:0x40 Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones); the memory will receive the following reset values after writing to the appropriate bit in the reset memory register: All fields will be zero; excluding the FID; each PF will receive 17 SB; 0-16 PF0; 17-33 PF1 .. 119-135 PF7. All the SB above 136 reset value is zero therefore thy are allocated to PF 0 also. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
38544
#define CAU_REG_SB_VAR_MEMORY 0x1c6000UL //Access:WB DataWidth:0x40 // Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones); the memory will receive the following reset values after writing to the appropriate bit in the reset memory register: All fields will be zero; excluding the FID; each PF will receive 17 SB; 0-16 PF0; 17-33 PF1 .. 119-135 PF7. All the SB above 136 reset value is zero therefore thy are allocated to PF 0 also.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
38544
#define CAU_REG_SB_VAR_MEMORY 0x1c6000UL //Access:WB DataWidth:0x40 // Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones); the memory will receive the following reset values after writing to the appropriate bit in the reset memory register: All fields will be zero; excluding the FID; each PF will receive 17 SB; 0-16 PF0; 17-33 PF1 .. 119-135 PF7. All the SB above 136 reset value is zero therefore thy are allocated to PF 0 also.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
38544
#define CAU_REG_SB_VAR_MEMORY 0x1c6000UL //Access:WB DataWidth:0x40 // Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones); the memory will receive the following reset values after writing to the appropriate bit in the reset memory register: All fields will be zero; excluding the FID; each PF will receive 17 SB; 0-16 PF0; 17-33 PF1 .. 119-135 PF7. All the SB above 136 reset value is zero therefore thy are allocated to PF 0 also.