Symbol: PRS_REG_ENCAPSULATION_TYPE_EN
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
39581
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL //Access:RW DataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
35967
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL //Access:RW DataWidth:0x6 Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
39085
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL //Access:RW DataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
39085
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL //Access:RW DataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
39085
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL //Access:RW DataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE