PRS_REG_CM_HDR_GFT
#define PRS_REG_CM_HDR_GFT 0x1f11c8UL //Access:RW DataWidth:0x14 // Multi Field Register.
#define PRS_REG_CM_HDR_GFT 0x1f11c8UL //Access:RW DataWidth:0x12 Multi Field Register. Chips: BB_B0 K2
#define PRS_REG_CM_HDR_GFT 0x1f11c8UL //Access:RW DataWidth:0x12 // Multi Field Register.
#define PRS_REG_CM_HDR_GFT 0x1f11c8UL //Access:RW DataWidth:0x12 // Multi Field Register.
#define PRS_REG_CM_HDR_GFT 0x1f11c8UL //Access:RW DataWidth:0x12 // Multi Field Register.