Symbol: BTB_REG_BIG_RAM_DATA
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
64403
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL //Access:WB DataWidth:0x80 // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
58803
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL //Access:WB DataWidth:0x80 Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
62192
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL //Access:WB DataWidth:0x80 // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
62192
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL //Access:WB DataWidth:0x80 // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
62192
#define BTB_REG_BIG_RAM_DATA 0xdb0c00UL //Access:WB DataWidth:0x80 // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.