BTB_REG_BIG_RAM_ADDRESS
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL //Access:RW DataWidth:0xc // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL //Access:RW DataWidth:0xb Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width. Chips: BB_A0 BB_B0 K2
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL //Access:RW DataWidth:0xb // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL //Access:RW DataWidth:0xc // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.
#define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL //Access:RW DataWidth:0xb // Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.