BRB_REG_TC_GUARANTIED_0
#define BRB_REG_TC_GUARANTIED_0 0x340900UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
#define BRB_REG_TC_GUARANTIED_0 0x340900UL //Access:RW DataWidth:0xd The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance. Chips: BB_A0 BB_B0 K2
#define BRB_REG_TC_GUARANTIED_0 0x340900UL //Access:RW DataWidth:0xd // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
#define BRB_REG_TC_GUARANTIED_0 0x340900UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.
#define BRB_REG_TC_GUARANTIED_0 0x340900UL //Access:RW DataWidth:0xd // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.