Symbol: BRB_REG_LB_TC_FULL_XON_THRESHOLD_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
50181
#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL //Access:RW DataWidth:0xe // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
46102
#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL //Access:RW DataWidth:0xd The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
48967
#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL //Access:RW DataWidth:0xd // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
48967
#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL //Access:RW DataWidth:0xe // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
48967
#define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL //Access:RW DataWidth:0xd // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.