PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478UL //ACCESS:W DataWidth:0x20 Description: Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register.
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL //Access:W DataWidth:0x20 // Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL //Access:W DataWidth:0x20 Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL //Access:W DataWidth:0x20 // Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL //Access:W DataWidth:0x20 // Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL //Access:W DataWidth:0x20 // Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.