PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR
#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR 0x2aa138UL //Access:W DataWidth:0x10 // Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it.
#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR 0x2aa138UL //Access:W DataWidth:0x10 Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR 0x2aa138UL //Access:W DataWidth:0x10 // Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it.
#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR 0x2aa138UL //Access:W DataWidth:0x10 // Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it.
#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR 0x2aa138UL //Access:W DataWidth:0x10 // Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it.