PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x946cUL //ACCESS:W DataWidth:0x8 Description: SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL //Access:W DataWidth:0x10 // SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL //Access:W DataWidth:0x10 SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL //Access:W DataWidth:0x10 // SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL //Access:W DataWidth:0x10 // SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL //Access:W DataWidth:0x10 // SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.