Symbol: PGLUE_B_REG_SR_IOV_DISABLED_REQUEST
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
11531
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030UL //ACCESS:R DataWidth:0x8 Description: SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44689
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL //Access:R DataWidth:0x10 // SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40593
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL //Access:R DataWidth:0x10 SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43684
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL //Access:R DataWidth:0x10 // SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43684
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL //Access:R DataWidth:0x10 // SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43684
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL //Access:R DataWidth:0x10 // SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.