Symbol: PGLUE_B_REG_PF_BAR1_SIZE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44986
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40890
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL //Access:RW DataWidth:0x4 For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43981
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43981
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43981
#define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M.