Symbol: PGLUE_B_REG_PF_BAR0_SIZE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44985
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40889
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL //Access:RW DataWidth:0x4 For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43980
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43980
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43980
#define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL //Access:RW DataWidth:0x4 // For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.