PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL //Access:R DataWidth:0x1a // Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2.
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL //Access:R DataWidth:0x1a Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL //Access:R DataWidth:0x1a // Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2.
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL //Access:R DataWidth:0x1a // Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2.
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL //Access:R DataWidth:0x1a // Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2.