Symbol: PGLUE_B_REG_INTERNAL_VFID_ENABLE
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
11867
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438UL //ACCESS:RW DataWidth:0x1 SPLIT:128 Description: Internal FID_enable configuration per-VF for master and target transactions.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44752
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x2aa168UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and target transactions. E4: split240.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40656
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x2aa168UL //Access:RW DataWidth:0x1 Internal FID_enable configuration per-VF for master and target transactions. E4: split240. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43747
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x2aa168UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and target transactions. E4: split240.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43747
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x2aa168UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and target transactions. E4: split240.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43747
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x2aa168UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and target transactions. E4: split240.