Symbol: PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
11865
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for target write transactions.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44754
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x2aa170UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write transactions. E4: split16.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40658
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x2aa170UL //Access:RW DataWidth:0x1 Internal FID_enable configuration per-PF for target write transactions. E4: split16. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43749
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x2aa170UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write transactions. E4: split16.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43749
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x2aa170UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write transactions. E4: split16.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43749
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x2aa170UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write transactions. E4: split16.