Symbol: PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
11861
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for master transactions.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44753
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x2aa16cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transactions. E4: split16.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40657
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x2aa16cUL //Access:RW DataWidth:0x1 Internal FID_enable configuration per-PF for master transactions. E4: split16. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43748
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x2aa16cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transactions. E4: split16.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43748
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x2aa16cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transactions. E4: split16.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43748
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x2aa16cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transactions. E4: split16.