Symbol: PGLUE_B_REG_INIT_DONE_PTT_GTT
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
44256
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL //Access:R DataWidth:0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
40104
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL //Access:R DataWidth:0x1 PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
43286
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL //Access:R DataWidth:0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
43286
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL //Access:R DataWidth:0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
43286
#define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL //Access:R DataWidth:0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.