PGLUE_B_REG_FLR_REQUEST_VF_95_64
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020UL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x2aa028UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x2aa028UL //Access:R DataWidth:0x20 FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x2aa028UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x2aa028UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x2aa028UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.