PGLUE_B_REG_FLR_REQUEST_VF_63_32
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901cUL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x2aa024UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x2aa024UL //Access:R DataWidth:0x20 FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x2aa024UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x2aa024UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x2aa024UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.