PGLUE_B_REG_FLR_REQUEST_VF_31_0
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018UL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x2aa020UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x2aa020UL //Access:R DataWidth:0x20 FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x2aa020UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x2aa020UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x2aa020UL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.