PGLUE_B_REG_FLR_REQUEST_VF_127_96
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024UL //ACCESS:R DataWidth:0x20 Description: FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x2aa02cUL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x2aa02cUL //Access:R DataWidth:0x20 FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. Chips: BB_A0 BB_B0 K2
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x2aa02cUL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x2aa02cUL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x2aa02cUL //Access:R DataWidth:0x20 // FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.