NIG_REG_TX_LB_GLBRATELIMIT_CTRL
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL //Access:RW DataWidth:0x3 // Multi Field Register.
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL //Access:RW DataWidth:0x3 Multi Field Register. Chips: BB_A0 BB_B0 K2
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL //Access:RW DataWidth:0x3 // Multi Field Register.
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL //Access:RW DataWidth:0x3 // Multi Field Register.
#define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL //Access:RW DataWidth:0x3 // Multi Field Register.