Symbol: NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
55286
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL //Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
50632
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL //Access:RW DataWidth:0x20 Specify the upper bound that credit register 0 is allowed to reach. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
53821
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL //Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
53821
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL //Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
53821
#define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL //Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.