Symbol: NIG_REG_RX_TC0_PRIORITY_MASK
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
55069
#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when the corresponding mask bit is 1. More than one bit may be set, allowing multiple priorities to be mapped to one TC.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
50415
#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL //Access:RW DataWidth:0x10 Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when the corresponding mask bit is 1. More than one bit may be set, allowing multiple priorities to be mapped to one TC. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
53604
#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when the corresponding mask bit is 1. More than one bit may be set, allowing multiple priorities to be mapped to one TC.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
53604
#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when the corresponding mask bit is 1. More than one bit may be set, allowing multiple priorities to be mapped to one TC.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
53604
#define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL //Access:RW DataWidth:0x10 // Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when the corresponding mask bit is 1. More than one bit may be set, allowing multiple priorities to be mapped to one TC.