NIG_REG_PRIORITY_FOR_TC_0
#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL //Access:RW DataWidth:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit for each priority.
#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL //Access:RW DataWidth:0x10 Flow control priorities used for each TC. This register is bit-mapped with one bit for each priority. Chips: BB_A0 BB_B0 K2
#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL //Access:RW DataWidth:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit for each priority.
#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL //Access:RW DataWidth:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit for each priority.
#define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL //Access:RW DataWidth:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit for each priority.