Symbol: NIG_REG_LLH_FUNC_TAG_VALUE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
55023
#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. These bits specify the value for comparison. There are 4 of this register per port per function. Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
50369
#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL //Access:RW DataWidth:0x10 This is a per-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. These bits specify the value for comparison. There are 4 of this register per port per function. Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
53558
#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. These bits specify the value for comparison. There are 4 of this register per port per function. Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
53558
#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. These bits specify the value for comparison. There are 4 of this register per port per function. Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
53558
#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. These bits specify the value for comparison. There are 4 of this register per port per function. Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN.