Symbol: NIG_REG_LLH_ENG_CLS_ENG_ID_TBL
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
55040
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL //Access:WB DataWidth:0x40 // 64-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated with the index to be routed to engine 1. Otherwise, the packet is routed to engine 0. This register is used only in the single-port with dual engine mode.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
50386
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL //Access:WB DataWidth:0x40 64-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated with the index to be routed to engine 1. Otherwise, the packet is routed to engine 0. This register is used only in the single-port with dual engine mode. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
53575
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL //Access:WB DataWidth:0x40 // 64-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated with the index to be routed to engine 1. Otherwise, the packet is routed to engine 0. This register is used only in the single-port with dual engine mode.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
53575
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL //Access:WB DataWidth:0x40 // 64-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated with the index to be routed to engine 1. Otherwise, the packet is routed to engine 0. This register is used only in the single-port with dual engine mode.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
53575
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL //Access:WB DataWidth:0x40 // 64-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated with the index to be routed to engine 1. Otherwise, the packet is routed to engine 0. This register is used only in the single-port with dual engine mode.