NIG_REG_LLH_CLS_TYPE_DUALMODE
#define NIG_REG_LLH_CLS_TYPE_DUALMODE 0x501964UL //Access:RW DataWidth:0x2 // Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise. Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found.
#define NIG_REG_LLH_CLS_TYPE_DUALMODE 0x501964UL //Access:RW DataWidth:0x2 Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise. Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found. Chips: BB_A0 BB_B0 K2
#define NIG_REG_LLH_CLS_TYPE_DUALMODE 0x501964UL //Access:RW DataWidth:0x2 // Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise. Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found.
#define NIG_REG_LLH_CLS_TYPE_DUALMODE 0x501964UL //Access:RW DataWidth:0x2 // Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise. Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found.
#define NIG_REG_LLH_CLS_TYPE_DUALMODE 0x501964UL //Access:RW DataWidth:0x2 // Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise. Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found.