NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0
#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this register should be programmed only while this rate limiter is disabled.
#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL //Access:RW DataWidth:0x20 Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this register should be programmed only while this rate limiter is disabled. Chips: BB_A0 BB_B0 K2
#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this register should be programmed only while this rate limiter is disabled.
#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this register should be programmed only while this rate limiter is disabled.
#define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of 25MHz clock cycles. Note that this register should be programmed only while this rate limiter is disabled.