MSEM_REG_DBG_FORCE_FRAME
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL //Access:RW DataWidth:0x4 DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift). Chips: BB_A0 BB_B0 K2
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
#define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).