MISC_REG_RESET_PL_UA
#define MISC_REG_RESET_PL_UA 0x008050UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] reserved;
#define MISC_REG_RESET_PL_UA 0x008050UL //Access:RW DataWidth:0x20 Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] reserved; Chips: BB_A0 BB_B0 K2
#define MISC_REG_RESET_PL_UA 0x008050UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] rst_n_misc_rbc_vaux_pd_ars;
#define MISC_REG_RESET_PL_UA 0x008050UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] reserved;
#define MISC_REG_RESET_PL_UA 0x008050UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] reserved;