MISC_REG_RESET_PL_PDA_VMAIN_2
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_psdm; [8] rst_ysdm; [9] rst_msem
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL //Access:RW DataWidth:0x20 Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_ysdm; [8] rst_psdm; [9] rst_msem; [10] rst_ysem; [11] rst_psem; [12] rst_xyld; [13] rst_tmld; [14] rst_muld; [15] rst_yuld; [16] rst_rdif; [17] rst_tdif; [18] rst_rss; [19] rst_cau; [20] rst_ptu; [21] rst_prm; [22] rst_rbcy; [23] rst_rbcq; [24] rst_rbcm; [25] rst_rbcb; [26] rst_rbcv; [27-31] reserved. Chips: BB_A0 BB_B0 K2
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_ysdm; [8] rst_psdm; [9] rst_msem; [10] rst_ysem; [11] rst_psem; [12] rst_xyld; [13] rst_tmld; [14] rst_muld; [15] rst_yuld; [16] rst_rdif; [17] rst_tdif; [18] rst_rss; [19] rst_cau; [20] rst_ptu; [21] rst_prm; Temporary comment: bit[20] rst_ptu isn't used (see temporary comment for pl_hv).
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_psdm; [8] rst_ysdm; [9] rst_msem; [10] rst_psem; [11] rst_ysem; [12] rst_xyld; [13] rst_tmld; [14] rst_muld; [15] Reserved; [16] rst_rdif; [17] rst_tdif; [18] rst_rss; [19] rst_cau; [20] rst_ptu; [21] rst_prm; [22] rst_rbcy; [23] rst_rbcq; [24] rst_rbcm; [25] rst_rbcb; [26] rst_rbcv; [26] rst_ypld; [27] rst_ptld; [28] rst_rgfs; [26] rst_tgfs; [31] Reserved.
#define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_psdm; [8] rst_ysdm; [9] rst_msem; [10] rst_psem; [11] rst_ysem; [12] rst_xyld; [13] rst_tmld; [14] rst_muld; [15] rst_yuld; [16] rst_rdif; [17] rst_tdif; [18] rst_rss; [19] rst_cau; [20] rst_ptu; [21] rst_prm; [22] rst_rbcy; [23] rst_rbcq; [24] rst_rbcm; [25] rst_rbcb; [26] rst_rbcv; [27-31] reserved. Temporary comment: bit[20] rst_ptu isn't used (see temporary comment for pl_hv), i.e. it is reserved.