MISC_REG_RESET_PL_PDA_VMAIN_1
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL //Access:RW DataWidth:0x20 Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10] rst_btb; [11] rst_pbf_pb1; [12] rst_pbf_pb2; [13] rst_rpb; [14] rst_rbcu; [15] rst_pbf; [16] rst_qm; [17] rst_tm; [18] rst_dorq; [19] rst_xcm; [20] rst_xsdm; [21] rst_xsem; [22] rst_rbct; [23] rst_cdu; [24] rst_ccfc;[25] rst_tcfc;[26] rst_rbcp; [27] rst_igu; [28] rst_dmae; [29] rst_semi_rtc;. Chips: BB_A0 BB_B0 K2
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10] rst_btb; [11] rst_pbf_pb1; [12] rst_pbf_pb2; [13] rst_rpb; [14] rst_rbcu; [15] rst_pbf; [16] rst_qm; [17] rst_tm; [18] rst_dorq; [19] rst_xcm; [20] rst_xsdm; [21] rst_xsem; [22] rst_rbct; [23] rst_cdu; [24] rst_ccfc;[25] rst_tcfc;[26] rst_rbcp; [27] rst_igu; [28] rst_dmae; [29] rst_semi_rtc;.
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10] rst_btb; [11] rst_pbf_pb1; [12] rst_pbf_pb2; [13] rst_rpb; [14] rst_rbcu; [15] rst_pbf; [16] rst_qm; [17] rst_tm; [18] rst_dorq; [19] rst_xcm; [20] rst_xsdm; [21] rst_xsem; [22] rst_rbct; [23] rst_cdu; [24] rst_ccfc;[25] rst_tcfc;[26] rst_rbcp; [27] rst_igu; [28] rst_dmae; [29] rst_semi_rtc;.
#define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10] rst_btb; [11] rst_pbf_pb1; [12] rst_pbf_pb2; [13] rst_rpb; [14] rst_rbcu; [15] rst_pbf; [16] rst_qm; [17] rst_tm; [18] rst_dorq; [19] rst_xcm; [20] rst_xsdm; [21] rst_xsem; [22] rst_rbct; [23] rst_cdu; [24] rst_ccfc;[25] rst_tcfc;[26] rst_rbcp; [27] rst_igu; [28] rst_dmae; [29] rst_semi_rtc;.