MISC_REG_RESET_PL_PDA_VAUX
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] rst_bmbn;
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL //Access:RW DataWidth:0x20 Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] rst_bmbn; Chips: BB_A0 BB_B0 K2
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [4] rst_xmac; [5] rst_xmac_soft; [6] rst_mstat_nw;
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] rst_bmbn;
#define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL //Access:RW DataWidth:0x20 // Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] rst_bmbn;