MISC_REG_RESET_PL_HV
#define MISC_REG_RESET_PL_HV 0x008060UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc; [5] rst_clk_pb;
#define MISC_REG_RESET_PL_HV 0x008060UL //Access:RW DataWidth:0x20 Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc; Chips: BB_A0 BB_B0 K2
#define MISC_REG_RESET_PL_HV 0x008060UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc; Temporary comment: bit[4] rst_atc is used to reset both ATC and PTU. As consequence the privilege of PTU reset is HV instead of PDA.
#define MISC_REG_RESET_PL_HV 0x008060UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc; [5] rst_clk_pb;
#define MISC_REG_RESET_PL_HV 0x008060UL //Access:RW DataWidth:0x20 // Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc; Temporary comment: bit[4] rst_atc is used to reset both ATC and PTU. As consequence the privilege of PTU reset is HV instead of PDA.