Symbol: MISC_REG_OPTE_MODE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33754
#define MISC_REG_OPTE_MODE 0x008c0cUL //Access:RW DataWidth:0x1 // 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30246
#define MISC_REG_OPTE_MODE 0x008c0cUL //Access:RW DataWidth:0x1 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33722
#define MISC_REG_OPTE_MODE 0x008c0cUL //Access:RW DataWidth:0x1 // 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33722
#define MISC_REG_OPTE_MODE 0x008c0cUL //Access:RW DataWidth:0x1 // 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33722
#define MISC_REG_OPTE_MODE 0x008c0cUL //Access:RW DataWidth:0x1 // 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.