MISC_REG_GEN_PURP_CR0
#define MISC_REG_GEN_PURP_CR0 0xa97cUL //ACCESS:RW DataWidth:0x20 Description: Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR0 0x008c80UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR0 0x008c80UL //Access:RW DataWidth:0x20 Debug only: spare RW register reset by core reset. Chips: BB_A0 BB_B0 K2
#define MISC_REG_GEN_PURP_CR0 0x008c80UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR0 0x008c80UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.
#define MISC_REG_GEN_PURP_CR0 0x008c80UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by core reset.